The present invention relates to a planar semiconductor device with a planar structure having an annular metallic film in a peripheral area of a chip, which is applicable to a MOSFET, an insulated gate bipolar transistor, a MOS gate thyristor and the like.
FIG. 3 is a perspective view of a resin-molded semiconductor device sealed with a resin. A semiconductor chip 21 is joined to a lead frame 22 and is sealed with a resin 23. Reference numeral 24 designates a wire connecting the lead frame 22 to the semiconductor chip 21.
FIG. 4 is a partial plan view of a corner portion of a vertical MOSFET chip, which is an example of a planar semiconductor device. A source electrode 2 constituting a cell portion through which a current is conducted, a withstand voltage structure section 3 with a field plate structure, and a peripheral electrode 4 are seen through a passivation film 1 covering almost the entire surface of the chip. Generally, the peripheral electrode 4 has the same potential as a drain electrode on the reverse surface.
FIG. 5 is a partial sectional view taken along line 5xe2x80x945 in FIG. 4. The left side of this view is a peripheral portion, the right side is the cell portion, and an intermediate withstand voltage structure is omitted. First, the cell portion is described. A p base region 6 is selectively formed on a surface layer of an n drift layer 5 with high resistivity. An n+ source region 7 is formed inside the p base region 6, and the source electrode 2 is formed in contact with surfaces of both the p base region 6 and the n+ source region 7. A gate electrode 9 is provided, via a gate oxide film 8, on the surface of the p base region 6 sandwiched by an exposed surface portion of the n drift layer 5 and the n+ source region 7. Reference numeral 10 designates an interlayer insulation film for insulating the gate electrode 9 and the source electrode 2. Reference numeral 1 denotes a passivation film.
In the peripheral portion of the chip, a p+ peripheral region 12 is formed on a surface layer of the n drift layer 5, the peripheral electrode 4 is formed in contact with a surface of the p+ peripheral region 12, and the passivation film 1 covers the peripheral electrode 4. The peripheral electrode 4 has a potential equal to that of a drain electrode (not shown) and is extended over a thick field oxide film 13 constituting the withstand voltage structure section to form a channel stopper. The peripheral electrode 4 and the source electrode 1 are typically comprised of an aluminum alloy containing silicon.
The corner portion of a rectangular MOSFET chip, particularly an inside of the corner portion, is normally shaped to have a curvature (this shape is hereafter referred to as a xe2x80x9ccurved shapexe2x80x9d) instead of a pattern with an acute angle, in order to weaken the electric field in the chip if a voltage is applied in an off-condition.
In the corner portion in FIG. 4, the outer end of the source electrode 2, the inside of the withstand voltage structure section 3 and the peripheral electrode 4 are formed into curved shapes, that is, quarter-circular arcs.
The outside of the outer end of the peripheral electrode 4, however, is often formed to have an almost right-angle corner instead of a curved shape in order to maintain contact with the peripheral region 12 and to stably apply a voltage to the drain electrode. Thus, the width of the corner portion of the peripheral electrode 4 is about three times larger than that of the straight portion.
The results on high-temperature and high-humidity reliability tests on such chips, however, indicate that in some chips, the withstand voltage characteristic becomes degraded. When such a degraded chip is examined, cracks are found in the passivation film 1 of the element, and many of them are present in the outer peripheral portions and corner portions of the chip.
This is because stress is concentrated on the outer peripheral portions and corner portions of the chip and because the cracks are developed as a result of thermal stress originating from a heat cycle or a power cycle. In particular, for a molded element comprising a chip sealed with a resin, stress concentration is severe due to an additional residual stress in the resin. Another reason is a large difference in thermal expansion coefficient between the aluminum alloy constituting the peripheral electrode and silicon nitride constituting the passivation film.
When such a semiconductor device is placed in a high-temperature and high-humidity environment, the atmosphere around the chip or moisture in the resin enters through the cracks into the passivation film. On the other hand, the cracks may develop and cause the passivation film to peel off, thereby exposing an aluminum electrode in the underlayer, which reacts with moisture in the atmosphere. The aluminum alloy electrode corrodes due to local battery action or the like, degrading the withstand voltage characteristic of the semiconductor device.
In view of this problem, it is an object of the present invention to provide a reliable semiconductor device by preventing cracks, particularly in the portions of the passivation film located in the chip corners.
To attain the object, the present invention provides a planar semiconductor device having a metallic film in the form of a closed ring in a peripheral area of a square semiconductor chip. The metallic film is covered with a passivation film. The width of a portion of the metallic film located in each corner portion of the chip in a chip-diagonal direction is almost the same as the width of each straight portion of the metallic film.
The most common shape of the metallic film is, for example, a partial annular ring.
This configuration reduces the difference in thermal expansion between the passivation film and the metallic film to prevent formation of cracks in the chip corner portions.
In particular, in a semiconductor device sealed with a molding resin, stress concentration due to residual stress or the like in the molding resin is likely to cause cracks. The above configuration, however, alleviates the stress concentration.